The exemplary embodiments relate to electronic design automation and, more particularly, relate to routing nets of an integrated circuit design with an emphasis on routability.
Advances in semiconductor technology presently make it possible to integrate hundreds of millions of transistors onto a single semiconductor chip. This dramatic increase in semiconductor integration densities has made it considerably more challenging to efficiently design circuits.
Specifically, routing a circuit design involves determining routes for metal wires which electrically connect circuit elements to produce routed circuits that perform desired functions. Routing wires of a large circuit design can take several days using conventional routing techniques. Moreover, traditional timing design closure may create a design which closes timing with Steiner models, but has large timing degradation post routing.
Physical synthesis is prominent in the automated design of integrated circuits such as high performance processors and application specific integrated circuits (ASICs). Physical synthesis is the process of concurrently optimizing placement, routing, timing, power consumption, crosstalk effects and the like in an integrated circuit design. This comprehensive approach helps to eliminate iterations between circuit analysis and place-and-route. Physical synthesis has the ability to resize gates (changing their gate sizes and power levels), insert repeaters (buffers or inverters), clone gates or other combinational logic, etc., so the area of logic in the design remains fluid. However, physical synthesis can take days to complete.
Routability is a key factor when performing circuit floorplanning or trying to close on timing via physical synthesis. A designer can expend considerable effort trying to get the design into a good state in terms of timing and signal integrity, only to subsequently find that it is unroutable. Ideally, the designer should be able to invoke a snapshot routability analysis that allows him or her to understand the routability issues involved from making floorplanning or optimization decisions.